Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate (PPPG)
نویسندگان
چکیده
منابع مشابه
Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)
Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This p...
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ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2012
ISSN: 0976-1527
DOI: 10.5121/vlsic.2012.3308